Research is ongoing in the area of complementary metal oxide semiconductor (CMOS) structures in the area of carrier mobility improvement. Some of the areas investigated for such improvements include the use of high-K gate dielectric materials with metal gate electrodes, the use of FinFET CMOS transistor structures, and the formation of strained materials in the channel of CMOS transistor and the use of liners to induce stress.
One approach to improving carrier mobility in CMOS structures, as discussed in, for example, Komoda et al.; “Mobility Improvement for 45 nm Node by Combination of Optimized Stress Control and Channel Orientation Design,” Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International 13-15 Dec. 2004 Page(s): 217-220, includes the use of silicon germanium, channel orientation and, liner layers.
Various of the approaches listed above are also discussed in, for example, Pidin et al.; “A Novel Strain Enhanced CMOS Architecture Using Selectively High Tensile and High Compressive Silicon Nitride Films,” Proc. IEDM 213-216 (2004) and in U.S. Pat. Nos. 6,885,084; 6,621,131; and 6,861,318.